View HM5116405S-5_649384.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HM5116405 Series HM5117405 Series
16 M EDO DRAM (4-Mword 4-bit) 4 k Refresh/2 k Refresh
ADE-203-633D (Z) Rev. 4.0 Nov. 1997 Description
The Hitachi HM5116405 Series, HM5117405 Series are CMOS dynamic RAMs organized 4,194,304-word 4-bit. They employ the most advanced CMOS technology for high performance and low power. The HM5116405 Series, HM5117405 Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They have package variations of standard 26-pin plastic SOJ and standard 26-pin plastic TSOP II.
Features
Single 5 V ( 10%) Access time: 50 ns/60 ns/70 ns (max) Power dissipation Active mode : 495 mW/440 mW/385 mW (max) (HM5116405 Series) : 550 mW/495 mW/440 mW (max) (HM5117405 Series) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) EDO page mode capability Long refresh period 4096 refresh cycles : 64 ms (HM5116405 Series) : 128 ms (L-version) 2048 refresh cycles : 32 ms (HM5117405 Series) : 128 ms (L-version) 3 variations of refresh -only refresh -beforeHidden refresh refresh
HM5116405 Series, HM5117405 Series
Battery backup operation (L-version) Test function 16-bit parallel test mode
Ordering Information
Type No. HM5116405S-5 HM5116405S-6 HM5116405S-7 HM5116405LS-5 HM5116405LS-6 HM5116405LS-7 HM5117405S-5 HM5117405S-6 HM5117405S-7 HM5117405LS-5 HM5117405LS-6 HM5117405LS-7 HM5116405TS-5 HM5116405TS-6 HM5116405TS-7 HM5116405LTS-5 HM5116405LTS-6 HM5116405LTS-7 HM5117405TS-5 HM5117405TS-6 HM5117405TS-7 HM5117405LTS-5 HM5117405LTS-6 HM5117405LTS-7 Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 300-mil 26-pin plastic TSOP II (TTP-26/24DA) Package 300-mil 26-pin plastic SOJ (CP-26/24DB)
2
HM5116405 Series, HM5117405 Series
Pin Arrangement
HM5116405S/LS Series HM5116405TS/LTS Series
VCC I/O1 I/O2
1 2 3 4 5
26 25 24 23 22 21
VSS I/O4 I/O3
VCC I/O1 I/O2
1 2 3 4 5
26 25 24 23 22 21
VSS I/O4 I/O3
A11
6
A9
A11
6
A9
A10 A0 A1 A2 A3 VCC
8 9 10 11 12 13
19 18 17 16 15 14 (Top view)
A8 A7 A6 A5 A4 VSS
A10 A0 A1 A2 A3 VCC
8 9 10 11 12 13
19 18 17 16 15 14 (Top view)
A8 A7 A6 A5 A4 VSS
Pin Description
Pin name A0 to A11 Function Address input Row/Refresh address Column address I/O1 to I/O4 Data input/Data output Row address strobe Column address strobe Write enable Output enable VCC VSS Power supply Ground A0 to A11 A0 to A9
3
HM5116405 Series, HM5117405 Series
Pin Arrangement
HM5117405S/LS Series HM5117405TS/LTS Series
VCC I/O1 I/O2
1 2 3 4 5
26 25 24 23 22 21
VSS I/O4 I/O3
VCC I/O1 I/O2
1 2 3 4 5
26 25 24 23 22 21
VSS I/O4 I/O3
NC
6
A9
NC
6
A9
A10 A0 A1 A2 A3 VCC
8 9 10 11 12 13
19 18 17 16 15 14
A8 A7 A6 A5 A4 VSS
A10 A0 A1 A2 A3 VCC
8 9 10 11 12 13
19 18 17 16 15 14
A8 A7 A6 A5 A4 VSS
(Top view)
(Top view)
Pin Description
Pin name A0 to A10 Function Address input Row/Refresh address Column address I/O1 to I/O4 Data input/Data output Row address strobe Column address strobe Write enable Output enable VCC VSS NC Power supply Ground No connection A0 to A10 A0 to A10
4
HM5116405 Series, HM5117405 Series
Block Diagram (HM5116405 Series)
Timing and control
A0 A1 to A9 * * * Column address buffers
Column decoder
4M array
4M array Row decoder * * * I/O buffers 4M array I/O1 to I/O4
Row address buffers
A10 A11
4M array
5
HM5116405 Series, HM5117405 Series
Block Diagram (HM5117405 Series)
Timing and control
A0 A1 to A10 * * * Column address buffers
Column decoder
4M array
4M array Row decoder * * * I/O buffers 4M array I/O1 to I/O4
Row address buffers
4M array
6
HM5116405 Series, HM5117405 Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70 C)
Parameter Supply voltage Input high voltage Input low voltage Note: Symbol VCC VIH VIL Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Note 1 1 1
1. All voltage referred to VSS.
7
HM5116405 Series, HM5117405 Series
DC Characteristics (Ta = 0 to +70 C, V CC = 5 V
10%, VSS = 0 V) (HM5116405 Series)
HM5116405 -5 -6 -- -- -7 Test conditions t RC = min TTL interface , = VIH Dout = High-Z CMOS interface , VCC - 0.2 V Dout = High-Z CMOS interface , VCC - 0.2 V Dout = High-Z t RC = min = VIH = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 s t RAS 0.3 s 0V Vin 7V -- --
Parameter Operating current*1 , * 2 Standby current
Symbol I CC1 I CC2
Min Max Min Max Min Max Unit -- -- 90 2 80 2 70 2 mA mA
--
1
--
1
--
1
mA
Standby current (L-version) -only refresh current*2 Standby current*
1
I CC2
--
150 --
150 --
150
A
I CC3 I CC5
-- --
90 5
-- --
80 5
-- --
70 5
mA mA
-beforecurrent
refresh
I CC6
-- -- --
90 80
-- --
80 70
-- --
70 65 350
mA mA A
EDO page mode current*1, * 3 I CC7 Battery backup current I CC10
350 --
350 --
Input leakage current Output leakage current Output high voltage Output low voltage
I LI I LO VOH VOL
-10 10 -10 10 2.4 0
-10 10 -10 10
-10 10 -10 10 VCC 0.4
A A V V
0 V Vin 7 V Dout = disable High Iout = -2 mA Low Iout = 2 mA
VCC 2.4 0.4 0
VCC 2.4 0.4 0
Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while = VIL. 3. Address can be changed once or less while = VIH.
8
HM5116405 Series, HM5117405 Series
DC Characteristics (Ta = 0 to +70 C, V CC = 5 V 10%, VSS = 0 V) (HM5117405 Series)
HM5117405 -5 Parameter Operating current* , * 2
1
-6 100 -- 2 --
-7 Test conditions t RC = min TTL interface , = VIH Dout = High-Z CMOS interface , VCC - 0.2 V Dout = High-Z CMOS interface , VCC - 0.2 V Dout = High-Z t RC = min = VIH = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z, CBR refresh: tRC = 62.5 s t RAS 0.3 s 0V Vin 7V -- --
Symbol I CC1 I CC2
Min Max Min Max Min Max Unit -- -- 90 2 80 2 mA mA
Standby current
--
1
--
1
--
1
mA
Standby current (L-version) -only refresh current*2 Standby current*1
I CC2
--
150 --
150 --
150
A
I CC3 I CC5
-- --
100 -- 5 --
90 5
-- --
80 5
mA mA
-beforecurrent
refresh
I CC6
-- -- --
100 -- 90 --
90 80
-- --
80 75 350
mA mA A
EDO page mode current*1, * 3 I CC7 Battery backup current I CC10
350 --
350 --
Input leakage current Output leakage current Output high voltage Output low voltage
I LI I LO VOH VOL
-10 10 -10 10 2.4 0
-10 10 -10 10
-10 10 -10 10 VCC 0.4
A A V V
0 V Vin 7 V Dout = disable High Iout = -2 mA Low Iout = 2 mA
VCC 2.4 0.4 0
VCC 2.4 0.4 0
Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while = VIL. 3. Address can be changed once or less while = VIH.
9
HM5116405 Series, HM5117405 Series
Capacitance (Ta = 25 C, V CC = 5 V 10%)
Parameter Input capacitance (Address) Input capacitance (Clocks) Symbol CI1 CI2 Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2
Output capacitance (Data-in, Data-out) CI/O
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. = VIH to disable Dout.
10
HM5116405 Series, HM5117405 Series
AC Characteristics (Ta = 0 to +70 C, VCC = 5 V 10%, VSS = 0 V) *1, *2 , *18
Test Conditions Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5116405/HM5117405 -5 Parameter Random read or write cycle time precharge time precharge time pulse width pulse width Row address setup time Row address hold time Column address setup time Column address hold time to delay time Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT Min 84 30 7 50 7 0 7 0 7 11 9 10 35 5 13 0 0 2 Max -- -- -- -6 Min 104 40 10 Max -- -- -- -7 Min 124 50 13 Max -- -- -- Unit ns ns ns Notes
10000 60 10000 10 -- -- -- -- 37 25 -- -- -- -- -- -- 50 0 10 0 10 14 12 13 40 5 15 0 0 2
10000 70 10000 13 -- -- -- -- 45 30 -- -- -- -- -- -- 50 0 10 0 13 14 12 13 45 5 18 0 0 2
10000 ns 10000 ns -- -- -- -- 52 35 -- -- -- -- -- -- 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4
to column address delay time hold time hold time to precharge time
to Din delay time delay time from Din delay time from Din Transition time (rise and fall)
11
HM5116405 Series, HM5117405 Series
Read Cycle
HM5116405/HM5117405 -5 Parameter Access time from Access time from Access time from address Access time from Read command setup time Read command hold time to Read command hold time from Read command hold time to Column address to Column address to to output in low-Z Output data hold time Output data hold time from Output buffer turn-off time Output buffer turn-off to to Din delay time Output data hold time from Output buffer turn-off to Output buffer turn-off to to Din delay time to Din delay time next delay time lead time lead time Symbol t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD t RNCD Min -- -- -- -- 0 0 50 0 25 15 0 3 3 -- -- 13 3 -- -- 13 13 50 Max 50 13 25 13 -- -- -- -- -- -- -- -- -- 13 13 -- -- 13 13 -- -- -- -6 Min -- -- -- -- 0 0 60 0 30 18 0 3 3 -- -- 15 3 -- -- 15 15 60 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -- -7 Min -- -- -- -- 0 0 70 0 35 23 0 3 3 -- -- 18 3 -- -- 18 18 70 Max 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 22 13 5 22 22 22 12 12 Notes 8, 9, 20 9, 10, 17, 20 9, 11, 17, 20 9, 20
12
HM5116405 Series, HM5117405 Series
Write Cycle
HM5116405/HM5117405 -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to Write command to Data-in setup time Data-in hold time lead time lead time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 7 7 7 7 0 7 Max -- -- -- -- -- -- -- -6 Min 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- -7 Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
Read-Modify-Write Cycle
HM5116405/HM5117405 -5 Parameter Read-modify-write cycle time to to delay time delay time delay time Symbol t RWC t RWD t CWD t AWD t OEH Min 111 67 30 42 13 Max -- -- -- -- -- -6 Min 135 79 34 49 15 Max -- -- -- -- -- -7 Min 161 92 40 57 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Column address to hold time from
Refresh Cycle
HM5116405/HM5117405 -5 Parameter Symbol Min 5 7 0 7 5 Max -- -- -- -- -- -6 Min 5 10 0 10 5 Max -- -- -- -- -- -7 Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
setup time (CBR refresh cycle) t CSR hold time (CBR refresh cycle) t CHR setup time (CBR refresh cycle) t WRP hold time (CBR refresh cycle) precharge to hold time t WRH t RPC
13
HM5116405 Series, HM5117405 Series
EDO Page Mode Cycle
HM51W16405/HM51W17405 -5 Parameter EDO page mode cycle time EDO page mode Access time from hold time from pulse width precharge Symbol t HPC t RASP t CPA Min Max 20 -- -- 28 3 7 5 28 -- -6 Min Max 25 -- 35 3 10 5 35 -- -7 Min Max 30 -- 40 3 13 5 40 -- Unit ns Notes 21 16 9, 17, 20
100000 -- 28 -- -- -- -- --
100000 -- 35 -- -- -- -- --
100000 ns 40 -- -- -- -- -- ns ns ns ns ns ns
precharge t CPRH low t DOH t COL t COP t RCHC
Output data hold time from hold time referred to setup time
9, 17
Read command hold time from precharge
EDO Page Mode Read-Modify-Write Cycle
HM5116405/HM5117405 -5 Parameter Symbol Min 57 45 Max -- -- -6 Min 68 54 Max -- -- -7 Min 79 62 Max Unit ns ns 14 Notes
EDO page mode read- modify-write t HPRWC cycle time delay time from precharge t CPW
Test Mode Cycle *19
HM5116405/HM5117405 -5 Parameter Test mode Test mode setup time hold time Symbol t WTS t WTH Min 0 7 Max -- -- -6 Min 0 10 Max -- -- -7 Min 0 10 Max -- -- Unit ns ns Notes
Refresh (HM5116405 Series)
Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 64 128 Unit ms ms Notes 4096 cycles 4096 cycles
14
HM5116405 Series, HM5117405 Series
Refresh (HM5117405 Series)
Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 32 128 Unit ms ms Notes 2048 cycles 2048 cycles
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing -only refresh or -beforerefresh). If -beforerefresh cycles are the internal refresh counter is used, a minimum of eight required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. V IH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + t CAC (max) tRAD + t AA (max). 11. Assumes that t RAD tRAD (max) and tRCD + t CAC (max) tRAD + t AA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to leading edge in early write cycles and to leading edge in delayed write or read-modify-write cycles. 16. t RASP defines pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, must disable output buffer prior to applying data to device. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M 4 are don't care during test mode. Test mode is set by performing a -and-before(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles.
15
HM5116405 Series, HM5117405 Series
To get out of test mode and enter a normal operation mode, perform either a regular beforerefresh cycle or -only refresh cycle. 20. In a test mode read cycle, the value of tRAC , t AA, t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 21. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode cycle (EDO read cycles. If both write and read operation are mixed in a EDO page mode cycle (tCAS + tCP + 2 tT) becomes greater page mode mix cycle (1), (2)), minimum value of than the specified t HPC (min) value. The value of cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). and . Data output turns off and becomes high impedance from later risting edge of Hold time and turn off time are specified by the timing specifications of later rising edge of and between t OHR and t OH , and between t OFR and t OFF. 22. Data output turns off and becomes high impedance from later rising edge of and . Hold time and turn off time are specified by the timing specifications of later rising edge of and between t OHR and t OH and between tOFR and t OFF. 23. XXX: H or L (H: V IH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
16
HM5116405 Series, HM5117405 Series
Timing Waveforms*23
Read Cycle
t RC t RAS t RP
t CSH t RCD tT t RSH t CAS
t CRP
t RAD t ASR t ASC
t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCHR t RCS t RCH
t WED t DZC t CDD t RDD Din High-Z
t DZO
t OEA
t OED
t CAC t AA t RAC t CLZ
t OEZ t OHO t OFF t OH t OFR t OHR t WEZ
Dout
Dout
Early Write Cycle
17
HM5116405 Series, HM5117405 Series
tRC tRAS tRP
tCSH tRCD tT tRSH tCAS
tCRP
tASR
tRAH
tASC
tCAH
Address
Row
Column
tWCS
tWCH
tDS
tDH
Din
Din
Dout
High-Z*
* t WCS
t WCS (min)
18
HM5116405 Series, HM5117405 Series
Delayed Write Cycle*18
t RC t RAS
t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS t ASR t RAH t ASC t CAH
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED
t DZO
OE t OEZ t CLZ High-Z Invalid Dout
Dout
19
HM5116405 Series, HM5117405 Series
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
tT t RCD t CAS t CRP
t RAD t ASR tRAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
t DZC t DS Din
High-Z
t DH
Din
t DZO
t OED t OEA
t OEH
t CAC t AA t RAC
t OEZ t OHO
High-Z
Dout t CLZ
Dout
-Only Refresh Cycle
20
HM5116405 Series, HM5117405 Series
t RC t RAS t RP
tT t CRP t RPC t CRP
t ASR Address t OFR t OFF Dout
t RAH Row
High-Z
21
HM5116405 Series, HM5117405 Series
-BeforeRefresh Cycle
t RC t RP t RAS t RP
t RPC
t CSR tT
t CHR
t RPC
t CRP
t CP
t WRP
t WRH
t CP
Address t OFR t OFF Dout High-Z
22
HM5116405 Series, HM5117405 Series
Hidden Refresh Cycle
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
tT t RSH t RCD t CHR t CRP
t RAD t ASR t RAH Address Row t ASC
t RAL t CAH
Column t RRH t RCH
t RCS
t RRH
t WRH t WRP
t WRP
tWRH
t DZC High-Z Din
t WED t CDD t RDD
t DZO t OEA
t OED
t CAC t AA t RAC t CLZ Dout Dout t OFR t OHR t OFF t OH
t OEZ t WEZ t OHO
23
HM5116405 Series, HM5117405 Series
EDO Page Mode Read Cycle
t RP t RASP t CP t CAS t RCS t RCHR t RCH t RCS t HPC t CAS t CP t HPC tCAS t RCHC t HPC t CPRH t CP t t CRP
t RNCD
tT
t CSH
RSH
tCAS t RRH t RCH
tASR Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din tDZO
High-Z tCOL tCOP tOED
tOEA tCAC tAA tRAC
tCPA tAA tCAC tWEZ tOEZ tOHO tOEA
tCPA tCPA tAA tCAC tDOH tAA tOEZ tCAC tOEA
tOFR tOHR tOEZ tOHO tOFF tOH Dout 4
tOHO Dout 3
Dout
Dout 1
Dout 2
Dout 2
24
HM5116405 Series, HM5117405 Series
EDO Page Mode Early Write Cycle
tRASP tRP
tT tRCD
tCSH tCAS tCP
tHPC tCAS tCP
tRSH tCAS tCRP
tASR
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
Address
Row
Column 1
Column 2
Column N
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
tDS
tDH
tDS
tDH
tDS
tDH
Din
Din 1
Din 2
Din N
Dout
High-Z*
* t WCS
t WCS (min)
25
HM5116405 Series, HM5117405 Series
EDO Page Mode Delayed Write Cycle*18
t RASP t RP
tT t CSH t RCD t CAS
t CP t HPC t CAS
t CP t RSH t CAS
t CRP
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL
t WP t DZC t DS t DH Din t DZO t OED t OEH Din 1 t DZO
t WP t DZC t DS t DH Din 2 t DZO t OED t OEH
t WP t DZC t DS t DH Din N t OED t OEH
t CLZ t OEZ Dout
Invalid Dout
t CLZ t OEZ
t CLZ t OEZ High-Z
Invalid Dout Invalid Dout
26
HM5116405 Series, HM5117405 Series
EDO Page Mode Read-Modify-Write Cycle*18
t RASP t RP
tT t CP t RCD t CAS
t HPRWC t CP t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD t RCS t CWL t ASC t CAH Column 2 t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t RCS
t WP t DZC t DS t DH
t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED
t WP t DZC t DS t DH Din N
Din t DZO t OED
Din 1 t DZO t OEH
t OEH
t OHO t AA t OEA t CAC t AA t CPA t OEZ t OEA t CAC
t OHO t AA t CPA t OEZ t OEA t CAC
t OHO
t RAC t CLZ Dout Dout 1
t CLZ
t CLZ
t OEZ High-Z
Dout 2
Dout N
27
HM5116405 Series, HM5117405 Series
EDO Page Mode Mix Cycle (1)
t RP t RASP t CRP tCAS tRSH t RCS tCPW tAWD t ASC tRAH Row tCAH tASC t CAH Column 2 t CAL tASC t CAH Column 3 t CAL t DS High-Z tOED t DH Din 3 tWED tWP t RAL t CAH Column 4 t CAL tRDD tCDD tRCS t RRH t RCH
tT t CAS t CSH t RCD t WCS tWCH
t CP t CAS
t CP tCAS
t CP
tASR Address
tASC
Column 1 t CAL
t DS Din
t DH Din 1
tCPA tAA tOEA tCAC Dout
tCPA tCPA tAA t OEZ tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
tCAC t OHO t DOH Dout 2
Dout 3
28
HM5116405 Series, HM5117405 Series
EDO Page Mode Mix Cycle (2)
t RNCD t RASP
t RP
tT
t CSH t CAS t RCD t RCS t RCHR t RCH tWCS t WCH t RCS t CAS
t CP tCAS
t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH
t CRP
t RRH t RCH
tASR Address Row
t ASC tRAH
tCAH
t ASC t CAH Column 2 t CAL t DS t DH Din 2 tOED tCOL
t ASC t CAH Column 3 t CAL
Column 1 t CAL
tRDD tCDD
Din
High-Z
tWED
tAA tOEA tCAC tRAC t OHO Dout Dout 1 tOEZ
t OEA tCPA tAA tCAC tOEZ t OHO
Dout 3
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
29
HM5116405 Series, HM5117405 Series
Test Mode Cycle *19
*,** Reset Cycle
Set Cycle**
Test Mode Cycle
Normal Mode
RAS
CAS
WE
* CBR or RAS-only refresh ** Address, Din, OE: H or L
30
HM5116405 Series, HM5117405 Series
Test Mode Set Cycle
t RC t RP t RAS t RP
t RPC
t CSR tT
t CHR
t RPC
t CRP
t CP
t WTS
t WTH
t CP
Address t OFR t OFF Dout High-Z
31
HM5116405 Series, HM5117405 Series
Package Dimensions
HM5116405S/LS Series HM5117405S/LS Series (CP-26/24DB)
Unit: mm
26
16.90 17.27 Max 21 19
14 0.13
1
0.26
68 0.74
13 0.12 0.80 +0.25 -0.17 6.79 - 0.18
Hitachi Code JEDEC EIAJ Weight (reference value) CP-26/24DB Conforms Conforms 0.8 g
+ 0.19
0.43 0.41
0.10 0.08
1.27
2.54
0.10
Dimension including the plating thickness Base material dimension
32
2.65
1.30 Max
3.50
8.51
HM5116405 Series, HM5117405 Series
HM5116405TS/LTS Series HM5117405TS/LTS Series (TTP-26/24DA)
Unit: mm
26
17.14 17.54 Max 21 19
14 7.62
1 0.42 0.40 0.08 0.06
68 1.27 0.21 M 1.15 Max
13 0.80 9.22 0.20 0.50 0.10 0.68 0 -5
1.20 Max
0.145 0.125
0.13
Hitachi Code JEDEC EIAJ Weight (reference value)
0.10
0.05 0.04
0.05
2.54
Dimension including the plating thickness Base material dimension
TTP-26/24DA Conforms -- 0.30 g
33
HM5116405 Series, HM5117405 Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447
Hitachi Europe GmbH Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30-00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
Copyright (c) Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
34
HM5116405 Series, HM5117405 Series
Revision Record
Rev. 1.0 2.0 Date Oct. 14, 1996 Nov. 8, 1996 Contents of Modification Initial issue Addition of HM5116405-5 Series Addition of HM5117405-5 Series Power dissipation (active) 550/495 mW(max) to 495/440/385 mW (max) (HM5116405 Series) 605/550 mW(max) to 550/495/440 mW (max) (HM5117405 Series) DC Characteristics (HM5116405 Series) I CC7 max: 110/100 mA to 80/70/65 mA DC Characteristics (HM5117405 Series) I CC1 I CC3 I CC6 I CC7 max: max: max: max: 110/100 mA to 100/90/80 mA 110/100 mA to 100/90/80 mA 110/100 mA to 100/90/80 mA 110/100 mA to 90/80/75 mA Drawn by Y. Kasama Y. Kasama Approved by M. Mishima Y. Matsuno
AC Characteristics t RCD min: 20/20 ns to 11/14/14 ns t RAD min: 15/15 ns to 9/12/12 ns t RSH min: 15/18 ns to 10/13/13 ns t RRH min: 0/0 ns to 5/5/5 ns t RWC min: 149/175 ns to 111/135/161 ns t RWD min: 82/95 ns to 67/79/92 ns t CWD min: 37/43 ns to 30/34/40 ns t AWD min: 52/60 ns to 42/49/57 ns t RPC min: 0/0 ns to 5/5/5 ns t HPRWC min: 79/90 ns to 57/68/79 ns Timing Waveforms Addition of t RNCD timing to EDO page mode mix cycle (2) 3.0 4.0 Feb. 27, 1997 Nov. 1997 AC Characteristics t RRH min: 5/5/5 ns to 0/0/0 ns Change of Subtitle Y. Kasama Y. Matsuno
35

▲Up To Search▲

Price & Availability of HM5116405S-5

	To Download HM5116405S-5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .